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CMM5104
November 1995
Radiation Hardened, High Reliability, CMOS/SOS 4096 Word by 1-Bit LSI Static RAM
Pinouts
18 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T18 TOP VIEW
A0 1 A1 2 A2 3 A3 4 A4 5 A5 6 DOUT 7 WE 8 VSS 9 18 VDD 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 DIN 10 CE
Features
* Radiation Hardened to 10K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s * Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Fully Static Operation * Single Power Supply 4.5V to 6.5V * All Inputs and Outputs TTL Compatible * Three-State Outputs * Industry Standard 18 Pin Configuration * Fast Access Time tAVQV = 200ns * Low Standby and Operating Power
Description
The CMM5104 is a high reliability 4096 word by 1-bit static random access memory using CMOS/SOS technology. It is designed for use in memory systems where low power and simplicity in use are desirable. CMOS/SOS technology permits operation in radiation environments. It is insensitive to neutrons, cannot latch up at any dose rate and is resistant to single event upset caused by cosmic rays or heavy ions. TTL compatibility on all input and output terminals permits easy system integration. The data out signal has the same polarity as the input data. A separate data input and a separate Three-state output are used. The CMM5104 is supplied in 18 lead dual-in-line sidebrazed ceramic package (D suffix). The part is also available in a 24 lead flatpack ceramic package (K suffix).
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F24 TOP VIEW
NC A0 A1 A2 A3 NC A4 A5 DOUT NC WE VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A6 A7 A8 NC NC A9 A10 A11 DIN NC CE
Ordering Information
PART NUMBER CMM5104K3 CMM5104D3 CMM5104K1DZ CMM5104D1DZ CMM5104D/Sample CMM5104K/Proto TEMP RANGE -55oC to +125oC PACKAGE Class B, 24 Lead Ceramic Flatpack (Not Rad Verified)
-55oC to +125oC Class B, 18 Lead SBDIP (Not Rad Verified) -55oC to +125oC Class S, 24 Lead Ceramic Flatpack (Rad Verified) -55oC to +125oC Class S, 18 Lead SBDIP (Rad Verified) 25oC -55oC to +125oC 18 Lead SBDIP 24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518736 3406.1
CMM5104 Functional Diagram
A11 A10 A9 A8 A7 A6 VDD VSS
TRANSITION DETECTORS, BUFFERS, AND ROW DECODER E
64 X 64 MEMORY MATRIX
SENSE AMPLIFIERS AND OUTPUT BUFFER
DATA OUT
POWER CONVERTER
E
TRANSITION DETECTORS, BUFFERS, AND COLUMN DECODER
DATA IN
WE AND CE DECODER (SEE TRUTH TABLE)
A0
A1
A2
A3
A4
A5
WE
CE
TRUTH TABLE CE H L L WE X L H MODE Not Selected Write Read OUTPUT High Z High Z Data Out
Spec Number 2
518736
Specifications CMM5104
Absolute Maximum Ratings
Supply Voltage (VDD), All voltage values referenced to VSS terminal . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC Typical Derating Factor. . . . . . . . . . .3.0mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 78oC/W 18oC/W Ceramic Flatpack Package . . . . . . . . . . . 80oC/W 20oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.64W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.63W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 12.5mW/oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5400 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +6.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD/2 to VDD Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS (NOTE 1) CONDITIONS VIN = 0V or VDD, VDD = 5.25V Cycle Time = 1s, VDD = 5.25V Cycle Time = 1s, VDD = 5.25V VOUT = 0.4V, VDD = 4.75V VOUT = VDD - 0.4V, VDD = 4.75V VDD = 4.75V VDD = 4.75V VIN = 0V or VDD, VDD = 5.25V Applied Voltage = 0V or VDD, VDD = 5.25V -55oC, +25oC MIN 4.0 -3 VDD/2 VDD = VDR MAX 0.1 4.5 0.1 0.8 2 5 2 40 +125oC MIN 2.5 -2 VDD/2 MAX 1.0 4.5 1.0 0.8 10 30 2.5 400 UNITS mA mA mA mA mA V V A A V A
PARAMETER Quiescent Device Current Operating Device Current (Note 2) Operating Device Current (Deselected) Output Low Drive (Sink) Current Output High Drive (Source) Current Input Low Voltage (Note 3) Input High Voltage (Note 3) Input Leakage Current Three-State Output Leakage Current Minimum Data Retention Voltage Data Retention Quiescent Current NOTES:
SYMBOL IDD IOPER IOPRD IOL IOH VIL VIH IIN IOZ VDR IDDDR
1. VDD = 5V 5%, VIN = 0V or VDD, Unless Otherwise Specified. 2. Operating current measured using 1MHz cycle and CL = 50pF. 3. Measured using 1MHz cycle. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) LIMITS -55oC, +25oC PARAMETER READ CYCLE TIMES Read Cycle Access from Address Access from CE WRITE CYCLE TIMES Write Cycle tAVAV 200 250 ns tAVAV tAVQV tELQV 200 200 220 250 250 280 ns ns ns SYMBOL MIN MAX MIN +125oC MAX UNITS
Spec Number 3
518736
Specifications CMM5104
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) (Continued) LIMITS -55 PARAMETER Write Pulse Width (Note 2) Address Set Up to Beginning of Write Address Set Up to End of Write Address Hold Time CE to Write Set Up Time CE Pulse Width (Note 1) Data to Write Set Up Time Data Hold From Write NOTES: 1. VDD = 4.75V. 2. CE and WE must overlap at least tWLWH minimum value, tDVWH minimum value must occur during this overlap. SYMBOL tWLWH tAVWL tAVWH tWHAV tELWH tELEH tDVWH tWHDX MIN 125 0 160 40 160 180 100 5
oC,
+25oC MAX MIN 145 0 205 45 205 220 120 10
+125oC MAX UNITS ns ns ns ns ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) LIMITS -55oC, +25oC PARAMETER Output Voltage Low Level Output Voltage High Level Input Capacitance (Note 2) Output Capacitance (Note 2) Output Hold From Address Output Hold From CE NOTE: 1. Parameters in this table are not directly 100% tested, but are characterized at initial design and after design or processing changes affecting these parameters. 2. Capacitance measurements are made with no bias applied. SYMBOL VOL VOH CIN COUT tAVQZ tEHQZ MIN VDD - 0.1 MAX 0.1 5 7 80 80 MIN VDD - 0.1 +125oC MAX 0.1 5 7 100 100 UNITS V V pF pF ns ns
TABLE 4. POST 10K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS POST RADIATION +25oC PARAMETER Quiescent Device Current Operating Device Current (Note 1) Operating Device Current (Deselected) Output Low Drive Current (Sink) Output High Drive Current (Source) Input Low Voltage (Note 2) Input High Voltage (Note 2) Input Leakage Current Three-State Output Leakage Current Minimum Data Retention Voltage Data Retention Quiescent Current SYMBOL IDD IOPER IOPRD IOL IOH VIL VIH IIN IOZ VDR IDDDR VDD = VDR CONDITIONS VIN = 0V or VDD, VDD = 5.25V Cycle Time = 1s, VDD = 5.25V Cycle Time = 1s, VDD = 5.25V VOUT = 0.4V, VDD = 4.75V VOUT = VDD - 0.4V, VDD = 4.75V VDD = 4.75V VDD = 4.75V VIN = 0V or VDD, VDD = 5.25V Applied Voltages = 0V or VDD, VDD = 5.25V MIN 2.5 2.0 VDD/2 MAX 1.0 4.5 1.0 0.8 10 30 2.5 400 UNITS mA mA mA mA mA V V A A V A
Spec Number 4
518736
CMM5104
TABLE 4. POST 10K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS POST RADIATION +25oC PARAMETER Read Cycle Access from Address Access from CE Write Cycle Write Pulse Width (Note 3) Address Set Up to Beginning of Write Address Set Up to End of Write Address Hold Time CE to Write Set Up Time CE Pulse Width (Note 3) Data to Write Set Up Time Data Hold From Write NOTES: 1. CE and WE must overlap for at least tWLWH minimum value, tDVWH minimum value must occur during this overlap. 2. Measured using 1MHz cycle. 3. Operating current measured using 1MHz cycle and CL = 50pF. SYMBOL tAVAV tAVQV tELQV tAVAV tWLWH tAVWL tAVWH tWHAV tELWH tELEH tDVWH tWHDX CONDITIONS VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V VDD = 4.75V MIN 250 250 145 0 205 45 205 220 120 10 MAX 250 280 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Quiescent Device Current Output Low Drive Current (Sink) Output High Drive Current (Source) Three-State Output Leakage Current SYMBOL IDD IOL IOH IOZ DELTA LIMITS +30A -15% of 0 hr. value -15% of 0 hr. value +500nA
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Group B (Optional) Group C (Optional) Group D (Optional) Group E, Subgroup 2 B5 Others METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 -IRZ SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7 N/A 1, 7, 9 1, 7, 9 3 SUBGROUPS 1, 7, 9 N/A 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 N/A
Spec Number 5
518736
CMM5104 Intersil - 3Z Product Flow
Radiation Verification (Each Wafer) Method 1019, 10K RADS (Si) Total Dose 2 Samples/Wafer, 0 Reject (3Z Product Flow continues below)
Intersil Space Level Product Flow -3 (Without Radiation Verification)
100% Internal Visual Inspection, Method 2010, Condition B or Alternate Condition B 100% Internal Visual Inspection, Method 2010, Condition B or Alternate Condition B 100% Temperature Cycle, Method 1010, Condition C 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Fine/Gross Leak, Method 1014 100% Initial Electrical Test, +25 C Optional High Temperature Stress, 48 Hours at (This is a Intersil option)
NOTES: 1. Failures from subgroups 1 and 7 are used for calculating PDA. The maximum allowable PDA is 5%. 2. Alternate Group A testing as allowed by MIL-STD-883, Method 5005 may be performed. 3. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
o
Optional Interim Electrical Test. (Only if the high temperature Stress was performed at Intersil' option.) 10% PDA 100% Static Burn-In, Method 1015, Condition A or B, 160 hours minimum, +125oC minimum (or equivalent time/ temperature per Method 1015) 100% Interim Electrical Test, 5% PDA, 3% PDA functional (Note 1) 100% Final Electrical Tests 100% External Visual, Method 2009
+125oC
Sample - Group A, Method 5005 (Note 2) Data Package Generation (Note 3)
Spec Number 6
518736
CMM5104 Intersil Space Level Product Flow -IDZ
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer), 2 Samples/Wafer, 0 Rejects Sample - Die Shear Monitor, Method 2019 or 2027 Sample - Wire Bond Monitor, Method 2011 100% Nondestructive Bond Pull, Method 2023 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% Serialization 100% Initial Test Optional High Temperature Stress Test, 48 Hours at +125oC (This is a Intersil option) Optional Interim Electrical Test (T0) (Only if the high temperature stress test was performed.) 10% PDA (Note 1)
NOTES: 1. If the optional 48-hour Stress Test is not utilized, then the initial test is used for T0 reference when calculating deltas. 2. Failures from Interim Electrical Tests T1 and T2 are combined for determining PDA. 3. Failures from subgroups 1, 7, and deltas are used for calculating PDA. The maximum allowable PDA is 5% with no more than 3% from subgroup 7. 4. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. Per Method 5004. 5. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 6. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, RAD Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Static Burn-In 1, Condition A or B, 24 hours minimum, +125oC minimum (or equivalent time/temperature), Method 1015 100% Interim Electrical Test (T1) and Deltas (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 Hours Minimum, +125oC minimum, (or equivalent time/temperature), Method 1015 100% Interim Electrical Test (T2) and Delta (T0-T2) (Note 2 and 3) 100% Dynamic Burn-In, Condition D, 240 hours at 125oC (or equivalent time/temperature), Method 1015 100% Interim Electrical Test (T3). 5% PDA All failures, Deltas (T0-T3) (Note 3) 100% Final Test, Method 5004 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 4) 100% External Inspection, Method 2009 Sample - Group A, Method 5005 (Note 5) 100% Data Package Generation (Note 6)
Spec Number 7
518736
CMM5104 Timing Waveforms
READ CYCLE
tAVAV A0 - A11 tAVQV CE tELQV tAVQZ tEHQZ OUTPUT DATA OUT WE tAVWL tWLWH tWHDX tDVWH DIN DATA VALID IN CE A0 - A11 tELWH tELEH (NOTE 2) tAVWH tWHAV
WRITE CYCLE
tAVAV
NOTE: Timing measurement is referenced to VDD/2.
NOTES: 1. Timing measurement is referenced to VDD/2. 2. CE and WE must overlap for at least TWLWH minimum value, tDVWH minimum value must occur during this overlap.
Typical Performance Curves
7.0 6 DEVICE CYCLE FREQUENCY (MHz) CL = 50pF 6.6 5 SUPPLY VOLTAGE (V) +25oC +125oC 3 6.2 5.8 +25oC +125oC FC = 1MHz, CL = 50pF
4
5.4 5.0
2
1 4.6 0 0 2 4 6 8 10 12 14 3.0 3.4 3.8 4.2 4.6 5.0 5.4 OPERATING DEVICE CURRENT (mA) 5.8
OPERATING DEVICE CURRENT (mA)
FIGURE 1. TYPICAL OPERATING DEVICE CURRENT (SELECTED) AS A FUNCTION OF CYCLE FREQUENCY
READ ACCESS FROM ADDRESS TIME (ns)
FIGURE 2. TYPICAL OPERATING DEVICE CURRENT (SELECTED) AS A FUNCTION OF SUPPLY VOLTAGE
375 325 300
VDD = 4.75V
+125oC
+25oC 275 250 225 200 0 100 200 LOAD CAPACITANCE (pF) 300
FIGURE 3. READ ACCESS FROM ADDRESS TIME (tAVQV) AS A FUNCTION OF LOAD CAPACITANCE (TIME MEASUREMENTS MADE AT 50% VDD POINT)
Spec Number 8
518736
CMM5104 Burn-In Circuits
VDD VDD R1 A0 R1 A1 R1 A2 R1 VDD A3 R1 A4 R2 R1 A5 R1 7 R1 R2 01 8 9 11 R1 10 12 6 13 R1 R1 A12 A13 R2 5 14 R1 A10 A11 4 15 R1 A9 R2 R1 6 R1 7 R1 8 9 11 R1 10 12 13 R1 R1 2 3 17 R1 16 R1 A8 A7 R1 VDD R1 5 14 R1 4 15 R1 1 18 R1 A6 R1 R1 1 R1 2 3 17 R1 16 R1 18 R1
DYNAMIC CONFIGURATION NOTES: R1 = 1k to 60k 5% R2 = 9.1kW 5% VDD = 5.5V (Min) VIN = 0V, VDD Frequency: A0 = 100kHz 5%; A1 = A0/2 . . . . A13 = A12/2 01 = 200kHz 5%, 0.6s Low, 4.4s High Ceramic DIP biasing shown. NOTES:
STATIC CONFIGURATION R1 = 1k to 60k 5% R2 = 9.1k 5% VDD = 5.5V (Min) Static Burn-In 1 memory array pre-initialized with all Highs at VDD, VIN = VDD Static Burn-In 2 memory array pre-initialized with all Lows at VSS, VIN = VSS Ceramic DIP biasing shown.
Irradiation Circuit
VDD
1 2 3 4 5 6 7 8 GND 9
18 17 16 15 14 13 12 11 10
NOTES: VDD = +5V, +5% GND = 0V All Resistors are 47k 5%
Spec Number 9
518736
CMM5104
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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